View ICS853111B_1786238.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low skew, 1-to-10, differential-to- 2.5v, 3.3v lvpecl/ecl fanout buffer ICS853111B idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 1 ICS853111By rev. b september 5, 2007 g eneral d escription the ICS853111B is a low skew, high perfor- mance 1-to-10 diff erential-to-2.5v/3.3v lvp ecl/ ecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from ics. the ICS853111B is characterized to operate from either a 2.5v or a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ICS853111B ideal for those clock distribution applications demanding well defined perfor- mance and repeatability. f eatures ? ten differential 2.5v/3.3v lvpecl / ecl outputs ? two selectable differential input pairs ? pclkx, npclkx pairs can accept the following differential input levels: lvpecl, lvds, cml, sstl ? maximum output frequency: >3ghz ? translates any single ended input signal to 3.3v lvpecl levels with resistor bias on npclk input ? output skew: 20ps (typical) ? part-to-part skew: 85ps (typical) ? propagation delay: 495ps (typical) ? jitter, rms: < 0.03ps (typical) ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -3.8v to -2.375v ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 32-lead tqfp, e-pad 7mm x 7mm x 1.0mm package body y package top view b lock d iagram p in a ssignment 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 q3 nq3 q4 nq4 q5 nq5 q6 nq6 v cco q7 nq7 q8 nq8 q9 nq9 v cco v cco nq2 q2 nq1 q1 nq0 q0 v cco ICS853111B q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 q8 nq8 q9 nq9 pclk0 npclk0 0 1 pclk1 npclk1 clk_sel v bb v cc clk_sel pclk0 npclk0 vbb pclk1 npclk1 v ee
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 2 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer t able 1. p in d escriptions t able 2. p in c haracteristics t able 3b. c ontrol i nput f unction t able t able 3a. c lock i nput f unction t able r e b m u ne m a ne p y tn o i t p i r c s e d 1v c c r e w o p. n i p y l p p u s e v i t i s o p 2l e s _ k l ct u p n in w o d l l u p . s t u p n i 1 k l c p n , 1 k l c p s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s t u p n i 0 k l c p n , 0 k l c p s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 30 k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 40 k l c p nt u p n in w o d l l u p / p u l l u p . t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i v c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 5v b b t u p t u o. e g a t l o v s a i b 61 k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 71 k l c p nt u p n in w o d l l u p / p u l l u p . t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i v c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 8v e e r e w o p. n i p y l p p u s e v i t a g e n 2 3 , 5 2 , 6 1 , 9v o c c r e w o p. s n i p y l p p u s t u p t u o 1 1 , 0 19 q , 9 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 1 , 2 18 q , 8 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 1 , 4 17 q , 7 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 7 16 q , 6 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 2 , 9 15 q , 5 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 2 2 , 1 24 q , 4 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 4 2 , 3 23 q , 3 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 2 , 6 22 q , 2 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 9 2 , 8 21 q , 1 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 3 , 0 30 q , 0 q nt u p t u o . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 5 7k r / c c v 2 s r o t s i s e r n w o d l l u p / p u l l u p 0 5k s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p x k l c px k l c p n9 q : 0 q9 q : 0 q n 01w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 10 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 0 ; d e s a i b 1 e t o n w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 ; d e s a i b 1 e t o n h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n ; d e s a i b 1 e t o n 0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i ; d e s a i b 1 e t o n 1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i o t t u p n i l a i t n e r e f f i d e h t g n i r i w " , n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n . " s l e v e l d e d n e e l g n i s t p e c c a s t u p n i l e s _ k l ce c r u o s d e t c e l e s 00 k l c p n , 0 k l c p 11 k l c p n , 1 k l c p
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 3 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer a bsolute m aximum r atings supply voltage, v cc 4.6v (lvpecl mode, v ee = 0) negative supply voltage, v ee -4.6v (ecl mode, v cc = 0) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5 v inputs, v i (ecl mode) 0.5v to v ee - 0.5v outputs, i o contin uous current 50ma surge current 100ma v bb sink/source, i bb 0.5ma operating temperature range, ta -40c to +85c storage temperature, t stg -65c to 150c package thermal impedance, ja 49.5c/w (0 lfpm) (junction-to-ambient) note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac characteris- tics is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v cc = 2.375v to 3.8v; v ee = 0v t able 4b. lvpecl dc c haracteristics , v cc = 3.3v; v ee = 0v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 23 . 38 . 3v i e e t n e r r u c y l p p u s r e w o p 0 2 1a m l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 1 . 25 7 2 . 28 3 . 25 2 2 . 25 9 2 . 27 3 . 25 9 2 . 23 3 . 25 6 3 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 0 4 . 15 4 5 . 18 6 . 15 2 4 . 12 5 . 15 1 6 . 14 4 . 15 3 5 . 13 6 . 1v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 7 0 . 26 3 . 25 7 0 . 26 3 . 25 7 0 . 26 3 . 2v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 4 . 15 6 7 . 13 4 . 15 6 7 . 13 4 . 15 6 7 . 1v v b b 2 e t o n ; e c n e r e f e r e g a t l o v t u p t u o 6 8 . 18 9 . 16 8 . 18 9 . 16 8 . 18 9 . 1v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 4 , 3 e t o n ; e g n a r e d o m n o m m o c 2 . 13 . 32 . 13 . 32 . 13 . 3v i h i t u p n i t n e r r u c h g i h 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l 1 k l c p , 0 k l c p 0 1 -0 1 - 0 1 - a 1 k l c p n , 0 k l c p n 0 5 1 -0 5 1 - 0 5 1 - a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - v . d e t i m i l s i n o i t a r e p o t u p n i d e d n e - e l g n i s : 2 e t o n c c . e d o m l c e p v l n i v 3 v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 3 e t o n h i . 1 k l c p n , 1 k l c p d n a 0 k l c p n , 0 k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 4 e t o n v s i c c . v 3 . 0 +
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 4 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer t able 4c. lvpecl dc c haracteristics , v cc = 2.5v; v ee = 0v t able 4d. ecl dc c haracteristics , v cc = 0v; v ee = -3.8v to -2.375v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 3 . 15 7 4 . 18 5 . 15 2 4 . 15 9 4 . 17 5 . 15 9 4 . 13 5 . 15 6 5 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 0 6 . 05 4 7 . 08 8 . 05 2 6 . 02 7 . 05 1 8 . 04 6 . 05 3 7 . 03 8 . 0v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 7 2 . 16 5 . 15 7 2 . 16 5 . 15 7 2 . 16 5 . 1v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 6 . 05 6 9 . 03 6 . 05 6 9 . 03 6 . 05 6 9 . 0v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 4 , 3 e t o n ; e g n a r e d o m n o m m o c 2 . 15 . 22 . 15 . 22 . 15 . 2v i h i t u p n i t n e r r u c h g i h 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l 1 k l c p , 0 k l c p 0 1 -0 1 -0 1 -a 1 k l c p n , 0 k l c p n 0 5 1 -0 5 1 -0 5 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - v . d e t i m i l s i n o i t a r e p o t u p n i d e d n e - e l g n i s : 2 e t o n c c . e d o m l c e p v l n i v 3 v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 3 e t o n h i . 1 k l c p n , 1 k l c p d n a 0 k l c p n , 0 k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 4 e t o n v s i c c . v 3 . 0 + l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 2 1 . 1 -5 2 0 . 1 -2 9 . 0 -5 7 0 . 1 -5 0 0 . 1 -3 9 . 0 -5 0 0 . 1 -7 9 . 0 -5 3 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 9 8 . 1 -5 5 7 . 1 -2 6 . 1 -5 7 8 . 1 -8 7 . 1 -5 8 6 . 1 -6 8 . 1 -5 6 7 . 1 -7 6 . 1 -v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 -4 9 . 0 -v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 -v v b b 2 e t o n ; e c n e r e f e r e g a t l o v t u p t u o 4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 -v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 4 , 3 e t o n ; e g n a r e d o m n o m m o c v e e v 2 . 1 +0v e e v 2 . 1 +0v e e v 2 . 1 +0v i h i t u p n i t n e r r u c h g i h 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l 1 k l c p , 0 k l c p 0 1 -0 1 -0 1 -a 1 k l c p n , 0 k l c p n 0 5 1 -0 5 1 -0 5 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - v . d e t i m i l s i n o i t a r e p o t u p n i d e d n e - e l g n i s : 2 e t o n c c . e d o m l c e p v l n i v 3 v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 3 e t o n h i . 1 k l c p n , 1 k l c p d n a 0 k l c p n , 0 k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 4 e t o n v s i c c . v 3 . 0 +
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 5 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer t able 5. ac c haracteristics , v cc = 0v; v ee = -3.8v to -2.375v or v cc = 2.375 to 3.8v; v ee = 0v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m f x a m y c n e u q e r f t u p t u o3 >3 >3 >z h g t d p 1 e t o n ; y a l e d n o i t a g a p o r p5 7 35 7 45 7 55 9 35 9 45 9 55 2 40 3 55 3 6s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o0 22 30 22 30 22 3s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p5 80 5 15 80 5 15 80 5 1s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r 3 0 . 03 0 . 03 0 . 0s p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 70 5 10 2 20 80 5 15 1 28 70 5 15 1 2s p d e r u s a e m e r a s r e t e m a r a p l l a . d e t o n e s i w r e h t o s s e l n u z h g 1 . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 6 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer a dditive p hase j itter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z input/output additive phase jitter at 155.52mhz = 0.03ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 - 140 -150 - 160 -170 -180 -190 1k 10k 100k 1m 10m 100m
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 7 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer p arameter m easurement i nformation o utput s kew d ifferential i nput l evel o utput l oad ac t est c ircuit scope qx nqx lvpecl v cc , v cco p art - to -p art s kew t sk(o) nqx qx nqy qy v cmr cross points v pp v cc v ee pclk0, pclk1 npclk0, npclk1 o utput r ise /f all t ime p ropagation d elay clock outputs 20% 80% 80% 20% t r t f v sw i n g t pd pclk0, pclk1 npclk0, npclk1 q0:q9 nq0:nq9 2v v ee t sk(o) nqx qx nqy qy part 1 part 2 -1.8v to -0.375v
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 8 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer a pplication i nformation figure 2a shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref ~ v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2a. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded lvcmos l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. single ended clock input v cc pclkx npclkx r1 c1 0.1u r2 1k 1k v_ref f igure 2b. s ingle e nded lvpecl s ignal d riving d ifferential i nput figure 2b shows an example of the differential input that can be wired to accept single ended lvpecl levels. the reference voltage level v bb generated from the device is connected to the negative input. the c1 capacitor should be located as close as possible to the input pin. w iring the d ifferential i nput to a ccept s ingle e nded lvpecl l evels clk_in c1 0.1uf vdd(or vcc) + - vbb
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 9 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. f igure 4a. h i p er c lock s pclk/npclk i nput d riven by a cml d river f igure 3b. h i p er c lock s pclk/npclk i nput d riven by an sstl d river f igure 3c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 3d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 3e. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm c2 r2 1k r5 100 zo = 50 ohm 3.3v 3.3v c1 r3 1k lvds r4 1k hiperclocks pclk npclk r1 1k zo = 50 ohm 3.3v pclk/npclk 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 10 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer i nputs pclk/npclk i nputs for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k resistor can be tied from pclk to ground. r ecommendations for u nused i nput and o utput p ins o utputs lvpecl o utputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating fre- quency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utputs f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 11 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer t ermination for 2.5v lvpecl o utput figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. r2 50 zo = 50 ohm vcco=2.5v r1 50 zo = 50 ohm + - 2.5v 2,5v lvpecl driv er f igure 5b. 2.5v lvpecl d river t ermination e xample vcco=2.5v r1 50 r2 50 zo = 50 ohm r3 18 2,5v lvpecl driv er zo = 50 ohm + - 2.5v f igure 5a. 2.5v lvpecl d river t ermination e xample r2 62.5 2.5v 2,5v lvpecl driv er r3 250 zo = 50 ohm zo = 50 ohm r4 62.5 2.5v + - r1 250 vcco=2.5v f igure 5c. 2.5v lvpecl t ermination e xample
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 12 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer s chematic e xample this application note provides general design guide using ICS853111B lvpecl buffer. figure 6 shows a schematic example of the ICS853111B lvpecl clock buffer. in this example, the f igure 6. e xample ICS853111B lvpecl c lock o utput b uffer s chematic input is driven by an lvpecl driver. clk_sel is set at logic high to select pclk0/npclk0 input. c4 0.1uf c6 (option) 0.1u zo = 50 r7 50 zo = 50 r2 50 vcc r1 50 vcc vcc=3.3v c7 (option) 0.1u r3 50 (u1-16) u1 ics853111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 vcc clk_sel pclk0 npclk0 vbb pclk1 npclk1 vee vcco nq9 q9 nq8 q8 nq7 q7 vcco nq6 q6 nq5 q5 nq4 q4 nq3 q3 vcco q0 nq0 q1 nq1 q2 nq2 vcco r4 1k zo = 50 c2 0.1uf (u1-9) r8 50 zo = 50 ohm c8 (option) 0.1u + - c5 0.1uf r10 50 r11 50 3.3v lvpecl + - vcc (u1-32) r13 50 c1 0.1uf zo = 50 ohm r9 50 c3 0.1uf (u1-25) vcc zo = 50 (u1-1) exposed pad expose metal pad (ground pad) ground plane solder signal trace signal trace therm al via solder m ask f igure 7. p.c. b oard for e xposed p ad t hermal r elease p at h e xample t hermal r elease p ath the expose metal pad provides heat transfer from the device to the p.c. board. the expose metal pad is ground pad connected to ground plane through thermal via. the exposed pad on the device to the exposed metal pad on the pcb is contacted through solder as shown in figure 7. for further information, please refer to the application note on surface mount assembly of amkor?s thermally /electrically enhance leadframe base package, amkor technology.
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 13 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS853111B. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS853111B is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.8v * 120ma = 456mw ? power (outputs) max = 30.94mw/loaded output pair if all outputs are loaded, the total power is 10 * 30.94mw = 309.4mw total power _max (3.8v, with all outputs switching) = 456mw + 309.4mw = 765.4mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.8c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.765w * 43.8c/w = 118.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 69.3c/w 57.8c/w 52.1c/w multi-layer pcb, jedec standard test boards 49.5c/w 43.8c/w 41.3c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6. t hermal r esistance ja for 32- pin tqfp, e-p ad f orced c onvection
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 14 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.935v (v cc_max - v oh_max ) = 0.935v ? for logic low, v out = v ol_max = v cco_max ? 1.67v (v cco_max - v ol_max ) = 1.67v pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco _max - v oh_max )) /r l ] * (v cco _max - v oh_max ) = [(2v - 0.935v)/50 ] * 0.935v = 19.92mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco _max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.67v)/50 ] * 1.67v = 11.02mw total power dissipation per output pair = pd_h + pd_l = 30.94mw q1 v out v cco rl 50 v cco - 2v f igure 7. lvpecl d river c ircuit and t ermination
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 15 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer r eliability i nformation t ransistor c ount the transistor count for ICS853111B is: 1340 pin compatible with mc100ep111 and mc100lvep111 t able 7. ja vs . a ir f low t able for 32 l ead tqfp, e-pad ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 69.3c/w 57.8c/w 52.1c/w multi-layer pcb, jedec standard test boards 49.5c/w 43.8c/w 41.3c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 16 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer -hd version heat slug down reference document: jedec publication 95, ms-026 t able 8. p ackage d imensions p ackage o utline - y s uffix for 32 l ead tqfp, e-pad n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 2 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 9 . 00 . 15 0 . 1 b 0 3 . 05 3 . 00 4 . 0 c 9 0 . 0- -0 2 . 0 e , d c i s a b 0 0 . 9 1 e , 1 d c i s a b 0 0 . 7 2 e , 2 d . f e r 0 6 . 5 3 e , 3 d 0 . 35 . 30 . 4 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 17 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer t able 9. o rdering i nformation while the information presented herein has been checked for both accur acy and reliability, integrate d device t echnology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t y b 1 1 1 3 5 8 s c iy b 1 1 1 3 5 8 s c id a p - e , p f q t d a e l 2 3y a r tc 5 8 o t c 0 4 - t y b 1 1 1 3 5 8 s c iy b 1 1 1 3 5 8 s c id a p - e , p f q t d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l y b 1 1 1 3 5 8 s c if l y b 1 1 1 3 5 8 s c id a p - e , p f q t d a e l 2 3 " e e r f d a e l "y a r tc 5 8 o t c 0 4 - t f l y b 1 1 1 3 5 8 s c if l y b 1 1 1 3 5 8 s c id a p - e , p f q t d a e l 2 3 " e e r f d a e l "l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
idt ? / ics ? 1-to-10, lvpecl/ecl fanout buffer 18 ICS853111By rev. b september 5, 2007 ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 9 7 1 . c 3 e r u g i f d e t c e r r o c . s w o r r e b m u n r e d r o / t r a p " e e r f d a e l " d e d d a 3 0 / 3 1 / 1 1 a 8 t 9 t 1 6 1 7 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f . 0 6 . 5 m o r f m m 5 . 3 d a e r o t 2 e / 2 d s n o i s n e m i d d e t c e r r o c - s n o i s n e m i d e g a k c a p d e d d a d n a g n i k r a m e e r f - d a e l d e t c e r r o c - e l b a t n o i t a m r o f n i g n i r e d r o . e t o n e e r f - d a e l 5 0 / 6 1 / 6 b c 4 t 8 t 4 0 1 6 1 v d e t c e r r o c - e l b a t s c i t s i r e t c a r a h c c d l c e p v l h i ) 5 8 @ ( . x a m . v 3 8 . 0 - m o r f v 6 5 . 1 d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r . 3 e / 3 d s n o i s n e m i d d e d d a - s n o i s n e m i d e g a k c a p 7 0 / 5 / 9
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. a ll other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ICS853111B low skew, 1-to-10, differential-to-2.5v, 3.3v lvpecl/ecl fanout buffer

▲Up To Search▲

Price & Availability of ICS853111B

	To Download ICS853111B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .